1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which buried wiring made of Cu or the like is formed in a low-k layer on a semiconductor substrate.
2. Background Art
In recent years, new micro patterning techniques have developed with high integration density and an improvement in capability of a semiconductor integrated circuit (to be referred to as an LSI hereinafter). Chemical-mechanical polishing (to be referred to as CMP hereinafter) is one of the new micro patterning techniques, and is used in LSI manufacturing steps, in particular, planarization of an interlayer dielectric film, formation of a metal plug, and formation of a buried wiring layer in a multi-level wiring (multi-level interconnection) process steps (for example, refer to U.S. Pat. No. 4,944,836).
Recently, in order to improve the capability of an LSI, conventional Al alloy has been replaced by Cu or Cu alloy (referred to generically as Cu hereinafter) as wiring material with low electrical resistance. However, Cu cannot be easily micropatterned by a dry etching method frequently used in fabrication of an Al-alloy wiring layer. Therefore, a Cu layer is deposited on an dielectric layer having a groove formed thereon, and the Cu layer is removed by CMP except for a portion buried in the groove to form a buried wiring layer. That is, a damascene method is mainly employed.
In order to reduce parasitic capacitance between wiring layers, an LSI in which, as an interlayer dielectric film, a low-k layer having the dielectric constant of 3.5 or less is used in place of an SiO2 layer having the dielectric constant k of about 4.2 has been practically used. Moreover, low-k materials, that is, low dielectric constant materials, having the dielectric constant of 2.5 or less have been also developed. As these low-k materials, porous materials having pores formed therein are often used. A conventional semiconductor device obtained by combining such a low-k layer or a porous low-k layer and a Cu wiring layer is shown in FIG. 11. A method of manufacturing the semiconductor device will be described below.
An underlying dielectric layer 2 made of a SiC layer is formed on a surface of a semiconductor substrate 1 by CVD method. A low-k layer 3 is formed on the underlying dielectric layer 2. A cap dielectric layer 4 is formed on the low-k layer 3 by CVD method. The cap dielectric layer 4 and the low-k layer 3 are patterned by photolithography and dry etching to form a groove. A barrier metal layer 5 and a Cu layer 6 are formed on the surface of the resultant structure to bury the groove. Finally, the Cu layer 6 and the barrier metal layer 5 on the cap dielectric layer 4 are removed by CMP to form a buried wiring layer in the groove. When a multi-level wiring (multi-level interconnection) is to be formed, the above processes are repeated.
However, since the mechanical strength of the low-k layer 3 is lower than that of an SiO2 layer, the low-k layer 3 is structurally damaged by polishing pressure of the CMP. Therefore, peeling disadvantageously occurs in the interface between the cap dielectric layer 4 and the low-k layer 3 or the interface between the low-k layer 3 and the underlying dielectric layer 2. The peeling especially occurs when a low-k material having a low elastic modulus and a low degree of hardness is used and when the adhesive strength between the cap dielectric layer and the low-k layer is low. In particular, it is reported that when the elastic modulus of the low-k layer is 5 GPa or less, peeling easily occurs (for example, refer to Simon Lin et al., “Low-k Dielectric Characterization for Damascene Integration”, 2001 IEEE, International Interconnect Technology Conference 2001, pp.146–148). As conventional countermeasures against the peeling, a polishing pressure of CMP is reduced, or a low-k layer having the high elastic modulus and a high degree of hardness is used.
However, when the polishing pressure is reduced as in the conventional technique, the polishing rate decreases to disadvantageously lower the throughput of CMP. Furthermore, when the low-k material having the high elastic modulus and a high degree of hardness is used, the dielectric constant k disadvantageously increases.